3D NAND retention: layer count is not a reliability rating

Published 11 October 2026 · Literature synthesis, not a device benchmark

A layer count describes structure, not a shelf life. To interpret a retention claim, identify the cell architecture, the age of the stored data and the conditions under which errors were counted.

Three design choices, not one label

KIOXIA's description of BiCS separates vertical cell organization from package stacking: electrodes and insulation form a stack, holes pass through it, and the cell structures are formed along those holes. Stacking completed dies in a package is not what makes the cells 3D NAND. [1]

Nor does 3D imply charge trap. Micron's August 2016 mobile 3D NAND announcement explicitly describes floating-gate technology. Its November 2020 announcement describes a transition to charge trap with replacement-gate architecture. These establish historical design choices, not a comparative reliability ranking. [2] [3]

Hesela's comparison checklist. The properties should be recorded separately.
Property	Question it answers	It does not establish
Vertical organization	Where are cells arranged?	Charge-storage material
Floating gate or charge trap	How is charge stored?	Bits encoded per cell
MLC, TLC or QLC	How many bits are encoded per cell?	A guaranteed error rate
Controller and ECC	How are observations recovered into data?	The raw medium's behavior by itself

What the 2018 retention experiment covers

Luo and colleagues tested several single-vendor 3D MLC chips at 20 degrees Celsius. Their retention experiment sampled 11 blocks per chip at wear levels from zero to 10,000 program/erase cycles and the first 72 pages per block, with nine observation times from seven minutes to 24 days. Results concern raw errors before correction; the read reference was optimized. [4, sections 4.1 and 4.3]

They observed rapid initial retention degradation, differences across layers, and dependence on neighboring cell state. For retention interference, the analysis selected neighbors programmed before the victim and excluded erased-state victims to reduce program-interference confounding. These controls matter: a neighbor-dependent result is not automatically evidence of a new mechanism. [4, sections 4.2-4.4]

The sample is not a cross-vendor fleet. Its exact chip count and layer count are not disclosed in the cited methodology. Figure 7 also includes model-extended portions, marked as dotted lines; do not treat every point as a measurement.

The overlooked distinction: two different clocks

HeatWatch examines both retention time after programming and dwell time between program/erase operations. Its 30- to 40-layer, single-vendor charge-trap characterization links dwell history and temperature to retention behavior and program variation. A special controller firmware exposes raw data without ECC; this is not an ordinary host-read benchmark. [5, sections 3.1-3.4]

Its dwell experiment used accelerated conditions at 70 degrees Celsius with a smaller room-temperature check. The temperature-conversion model fits an activation energy rather than assuming a planar-flash value transfers unchanged. This supports recording the thermal and cycling protocol, not heating an SSD to repair it. [5, sections 3.2 and 4.2]

The same RBER label can hide a different experiment. HeatWatch counts mismatches using the default read reference; the other study reports RBER at its optimum. [5, section 3.1] [4, section 4.1] Our inference: do not merge or rank their error curves without aligning the sensing policy, even when units and wear counts match.

Our inference: two tests with equal program/erase counts need not have equal histories. Record the intervals used to reach that count and the time since the final program operation separately. Drive power-on hours are not a substitute for either.

A trap is not always a defect

KIOXIA's reliability handbook describes intended storage on an isolated floating gate, but also unwanted oxide trapping and interface-state changes associated with endurance degradation. The word "trap" therefore needs its location and role: intentional charge storage in a charge-trap cell is not itself proof of damage. The handbook section concerns floating-gate devices; its failure description is not a quantitative model for every 3D structure. [6, section 2-1-7]

Our diagnostic rule is to name the mechanism before selecting a remedy. More sensing, stronger decoding and rewriting data are different interventions; evidence for one does not establish the need for another. See the separate analyses of read-retry and LDPC sensing and decoding costs.

A reproducible retention comparison

This reporting checklist is our synthesis, not a completed experiment:

Identify the NAND generation, charge-storage architecture and cell encoding. Mark proprietary details unknown.
Record chips, blocks, pages and bits examined, plus layer selection. Preserve per-chip results rather than treating every bit as an independent device.
Keep wear count, dwell history, retention age, stored patterns and temperature history separate.
Specify sensing settings and the error boundary: raw mismatches, failed codewords or host-visible outcomes.
Distinguish measured observations from fitted curves and accelerated-time conversions. Publish conversion assumptions and uncertainty.
Report failed reads and excluded samples. An average of successful reads alone cannot establish reliability.

This review does not reproduce the papers' error curves or evaluate their raw datasets. We have not run a hardware experiment, estimated current fleet failure rates or derived a universal refresh interval. Follow the device's supported operating limits and established backup procedures, not an improvised heating or forced-aging experiment.

Structured corpus: 3D NAND, charge-trap flash, floating gate, early retention loss, retention interference, layer-to-layer process variation and data retention.

Primary sources

Reviewed 11 October 2026, Europe/Warsaw. No third-party figures or datasets reproduced.