NOR Flash

NOR

Random reads, sector erasure and execute-in-place: what NOR makes convenient, and what firmware updates still have to handle.

Glossary entry on hesela.dev · JSON record · Execute-in-place

In one minute

NOR flash is non-volatile memory that supports fine-grained random reads, commonly used to hold firmware and, with a compatible memory path, execute code in place.

Treat read access and modification as separate contracts. NOR can provide byte or word reads, while programming and erasure operate under different rules. Infineon's FAQ describes programming from erased 1 bits toward 0 and restoring bits through sector or chip erase. A byte-readable address is therefore not an unrestricted byte-rewritable location. [1]

Program granularity also depends on the part: word programming and buffered or page programming are distinct interfaces. For the FL-S family discussed in Infineon's FAQ, repeated programming within one ECC unit can disable its automatic correction. The safe update unit comes from the data sheet, not merely the width of a CPU store. [1]

A subtle trap appears in the S29GL-T example: a second write may clear only data bits, yet recalculated hidden ECC parity can require a forbidden 0-to-1 transition and disable correction. Data-bit direction alone is therefore insufficient to approve repeated programming. Follow the family-specific ECC and erase rules. [1]

Execute-in-place (XIP) means fetching instructions directly from memory-mapped non-volatile storage, rather than loading those executable instructions into a separate RAM image. It does not mean that the system needs no RAM: Linux's cramfs documentation distinguishes directly mapped read-only segments from writable data copied into memory. Directly executed segments must be uncompressed and suitably aligned; this need not apply to the entire filesystem image. [3]

Serial NOR can support this execution path through a compatible memory controller. ST's AN4760 describes STM32 QUADSPI memory-mapped mode for reads and code execution, while indirect mode handles commands such as programming and erasing. Instruction, address, dummy-cycle and data settings must match the flash device. Caching and prefetch affect execution performance. [2]

The serial flash's continuous-read mode and the processor's XIP capability are related but different. AN4760's SIOO option reduces repeated command overhead when both sides support it; it is not the definition of XIP. Qualify the actual processor, controller and flash combination, including what happens when an update competes with instruction fetches. [2]

Compared to neighbors

Firmware code placement and flash-update design answer different questions. Plan both before selecting a device.

Separate access contracts; exact widths and command limits are part-specific.
Operation	Engineering check
Read	Address mapping and access latency
Program	Allowed update unit and ECC rules
Erase	Sector layout and data preservation

Uncertainty notes

Automatic-ECC restrictions cited here concern the named Infineon families, not every NOR device. AN4760 describes STM32 QUADSPI behavior rather than a universal controller specification.

Sources

01Infineon - NOR Flash FAQs, questions 2, 4, 9-10, 31, 36-39 and 57 · accessed 2026-10-18
02STMicroelectronics - AN4760 Rev 5, sections 3.3-3.4: QUADSPI modes and execution · accessed 2026-10-18
03Linux kernel documentation - Cramfs: memory-mapped image and execute-in-place · accessed 2026-10-18