NAND Flash

A NAND read has two stages: sensing cells into an internal page register, then transferring requested data over the interface. Programming loads data into a register before changing the array; erasing resets a larger block for reuse. These units explain why a host's small write cannot be treated as a direct overwrite of one arbitrary flash byte. [1]

An SSD adds address translation and reclamation around these constraints. A logical overwrite can be placed in a different physical page; surviving data must be preserved when reclaiming a block. The host's logical sector, the NAND page and the erase block are different units. [1]

A NAND page can include an out-of-band (OOB), or spare, area alongside its main data. That area carries ECC and other reserved information; it is not an extra pool of host-addressable blocks. Desnoyers warns that stronger ECC can leave less room for translation metadata, so an FTL must not assume that every spare byte is available. [4]

Choose who owns the management work. Raw NAND exposes responsibilities to the external controller or software stack. Fully managed NAND integrates a controller. On-die ECC occupies a narrower middle ground: correcting bits inside the device does not by itself provide wear leveling or bad-block management. [2]

For raw-NAND integration, preserve factory bad-block information, apply the required ECC scheme, inspect program/erase status, and retire blocks that fail as specified. A serial interface does not remove these obligations. Micron's guidance also describes loading NAND boot code into DRAM, rather than assuming the array behaves like directly executable NOR. [3]

Do not turn one generation's numbers into NAND constants. Desnoyers documents variation in geometry and the relationship between endurance and retention. Read the exact part's data sheet and qualification conditions before choosing ECC, planning spare capacity or estimating service life. [4]