Host Memory Buffer (HMB)

NVMe HMB

How host RAM supports a DRAM-less SSD, how HMB differs from controller memory, and what it does not tell you about speed or durability.

Glossary entry on hesela.dev · JSON record · Controller Memory Buffer · Mapping-cache analysis

In one minute

Host Memory Buffer is an optional NVMe feature that lets a controller use memory allocated by the host.

HMB changes where working memory is obtained. KIOXIA describes cooperation between the host driver and SSD controller, introduced with NVMe 1.2. Its BG4 diagram contrasts an onboard lookup table with one held in host DRAM. That is a documented implementation, not a requirement that all controllers organize their cache identically. [2] [3]

The host supplies memory ranges through the HMB Set Features command. NVMe 1.4a leaves their use vendor-specific and requires correct operation without an allocation. HMB is therefore optional working memory, not extra namespace capacity. [1]

A mapping entry identifies where user data is stored; it is not the user data itself. Micron explains that additional HMB can accommodate larger FTL tables and cache other information. Consequently, asking how much memory exists is only the start: ask what information is cached and how often the workload reuses it. [4]

Controller Memory Buffer (CMB) reverses the location: it is controller-resident memory exposed through PCIe, with supported uses advertised by the controller. It is not another name for HMB or for every internal DRAM chip. [1]

The preferred size advertised by a controller is not the actual allocation. In NVMe 1.4a, HMPRE and HMMIN use 4 KiB units, while HSIZE uses the configured controller memory page size (CC.MPS). Check enablement separately. [1]

For a useful comparison, record the SSD model, capacity, firmware, host software, HMB enablement and allocated size. Keep the access range, read/write mix, preconditioning and test duration comparable. These are proposed comparison controls, not a benchmark performed for this card.

A 2020 device study found mapping-cache evidence, but its fixed-allocation SSD-B did not permit the same size-sweep inference as SSD-A and SSD-C. [6]

Avoid translating a product example into a universal speed claim. The BG4 brief compares named devices under stated test conditions; it does not establish that every HMB drive equals every drive with onboard DRAM. A sequential headline alone cannot diagnose an address-mapping bottleneck. [3]

Memory location is not a durability certificate. Micron distinguishes protection of already-written data from protection of buffered, in-flight writes, including designs with and without onboard DRAM. Check the particular device's guarantee and the application's synchronization requirements. [5]

NVMe 1.4a requires HMB usage not to cause data loss or corruption during surprise removal. This is a conformance requirement, not evidence that a particular SSD passed a power-cut test. [1]

Compared to neighbors

Separate location, purpose and persistence before comparing SSD cache specifications.

HMB and neighboring memory concepts: what each description establishes

HMB: Relevant evidenceHost-allocated memory for controller use. [1]; Not establishedA fixed cache policy or speed rating.
CMB: Relevant evidenceController memory exposed for supported host uses. [1]; Not establishedThat every onboard DRAM buffer is a CMB.
Mapping cache: Relevant evidenceCached address-translation information. [4]; Not establishedThat user data is cached alongside every mapping.
Power-loss protection: Relevant evidenceA stated scope for stored data or in-flight writes. [5]; Not establishedA guarantee implied by a DRAM-less label.

HMB and neighboring memory concepts: what each description establishes
Concept	Relevant evidence	Not established
HMB	Host-allocated memory for controller use. [1]	A fixed cache policy or speed rating.
CMB	Controller memory exposed for supported host uses. [1]	That every onboard DRAM buffer is a CMB.
Mapping cache	Cached address-translation information. [4]	That user data is cached alongside every mapping.
Power-loss protection	A stated scope for stored data or in-flight writes. [5]	A guarantee implied by a DRAM-less label.

Uncertainty notes

Source-based engineering guide; no SSD, host driver or power-loss behavior was tested for this card.
Protocol statements are scoped to NVMe 1.4a. Vendor examples describe their named designs, not a universal performance ranking.
No invention date, fixed HMB size or operating-system support matrix is inferred.

In one minute

Compared to neighbors

Uncertainty notes

Sources