SSD mapping caches: why DRAM size is not a speed rating

12 October 2026 / Architecture review and computed examples

A mapping cache remembers where data lives, not necessarily the data itself. Its memory footprint, the frequency of translation misses and the survival of acknowledged writes are three different questions. DRAM capacity alone answers none of them.

The map is part of the storage system

An SSD's flash translation layer relates logical addresses to physical flash locations. Out-of-place updates and reclamation change those locations. Agrawal and colleagues distinguish the logical map from request buffering and explain why recovery must identify the newest surviving copy, not merely find readable pages. Their 2008 work uses trace-driven simulation, not measurements of today's drives. [1, sections 3-4]

That distinction matters when a specification says "cache." A data-buffer hit can avoid fetching user data. A mapping-cache hit resolves its location. Changing mapping granularity also changes placement freedom and partial-update work; a smaller table is not a free improvement. [1, section 3.1]

Calculate the representation before judging the capacity

For an invented flat map, let C be the logical capacity in bytes, G the bytes represented by one entry, E the entry payload in bytes and B the cache payload budget. The number of entries is ceil(C/G); the full-map payload is ceil(C/G)E. The cache holds at most min(floor(B/E), ceil(C/G)) entries.

Here G is a chosen mapping unit, not automatically the host sector size or the NAND page size. E is an explicit assumption, not a universal pointer width. Cache tags, replacement state, directories, validity information, alignment, compression and spare physical space are excluded.

Computed examples: G = 4 KiB, B = 64 MiB. One MiB = 2^20 bytes. One TB = 10^12 bytes; one TiB = 2^40 bytes. Not a product survey.
Logical capacity	Entry payload, B	Full map, MiB	Cached address span, GiB
1 TB	4	931.32	64
1 TB	8	1862.65	32
1 TiB	4	1024.00	64
1 TiB	8	2048.00	32
4 TiB	4	4096.00	64
4 TiB	8	8192.00	32

The 1 TiB, four-byte example needs exactly 1 GiB of map payload. The 1 TB example needs 976,562,500 bytes, about 931.32 MiB. Doubling E doubles the map. Increasing G from 4 to 16 KiB quarters its entry count for these capacities, but changes what each entry represents.

The 64 MiB budget can describe up to 64 GiB of logical addresses at G = 4 KiB and E = 4 B. That is a coverage calculation, not 64 GiB of cached user data, and not a prediction of a 6.25% hit ratio on the 1 TiB example. The complete 12-case dataset includes both granularities, exact bytes, input assumptions and reproducible code.

A translation miss can add another flash read

Demand-based designs retain mappings in flash translation pages and cache selected entries in memory. In the architecture described by LearnedFTL, a miss can require reading a translation page before reading the requested data. This is the translation-induced double-read problem. [2, section II]

Our deliberately small example uses an initially empty, two-entry LRU cache. Each number below identifies one mapping entry. Every lookup needs one data read; each miss adds exactly one translation read. There is no prefetch, shared translation-page cache, dirty eviction, data caching, concurrency or read retry.

Eight lookups per constructed trace; two cache slots. Counts include cold misses.
Reference string	Hits	Misses	Modeled NAND reads
0, 1, 0, 1, 0, 1, 0, 1	6	2	10
0, 1, 2, 3, 0, 1, 2, 3	0	8	16

The repeated pair has six hits; the four-entry cycle has none. Memory capacity alone therefore does not determine locality. Under these assumptions, reads per lookup equal 1 + misses/lookups: 1.25 versus 2. Those are event counts, not latency multipliers, hit-rate measurements or a faithful DFTL implementation.

The dependency-free evaluator generates both tables and is covered by regression tests. All inputs are constructed, so no sampling confidence interval applies. Uncertainty lies in whether the assumptions describe the system you want to understand.

An obscure but important evaluation boundary

LearnedFTL combines cached mappings with prediction guarded by a bitmap of exact predictions. Its HPCA 2024 evaluation uses FEMU with 32 GB logical capacity and 2 GB spare space, as labeled in the paper. Baselines are reimplemented and adapted; they are not unmodified original binaries. Retention-rewrite training is proposed but not exercised because the emulator lacks that mechanism. [2, sections III-IV]

These details qualify the comparison. The work demonstrates a research design; it does not establish the firmware, HMB policy or endurance of a retail SSD. We have not reproduced its benchmark or used its headline speedups as purchasing advice.

HMB changes where memory is available

In NVMe revision 1.4a, HMB gives a controller exclusive use of assigned host-memory ranges. Their use is vendor-specific; proper operation without an allocation is required. The interface is not restricted to a universal mapping-cache layout. [3, section 8.9]

KIOXIA's 2018 explanation describes using host DRAM in its DRAM-less BG-series architecture and the necessary cooperation with the host driver. Its performance equivalence statement is a vendor claim about that design, not a guarantee that every HMB SSD matches every onboard-DRAM SSD. [4]

For a comparison, record whether HMB is supported, enabled and actually allocated. Keep capacity, firmware, host software and access range fixed. Report the address distribution, preconditioning and read/write mix. These are proposed controls, not experiments performed for this article.

Neither DRAM nor HMB is a durability certificate

Micron's historical power-loss paper separates preservation of already stored data from protection of data still in flight, and describes mapping recovery and hold-up circuitry as additional mechanisms. Volatile DRAM itself does not provide that protection. Do not infer the persistence of an acknowledged write from the presence or absence of a DRAM chip. [5, p. 3]

Nor should HMB be described as permission to lose data: the cited NVMe revision explicitly requires protection against data loss or corruption on surprise removal while HMB is used. That is a specification requirement, not a power-cut test of a particular device. [3, section 8.9]

Continue with the power-loss protection guide. Machine-readable concepts: FTL, mapping cache, translation page and HMB.

Primary sources and scope

Sources checked 12 October 2026. Versioned specification and historical designs, not a latest-standard survey. No hardware benchmark, crash experiment, empirical failure rate or reproduced paper result. Source works retain their own rights.