Technology card
ShippingFlash Translation Layer (FTL)
Flash translation layer
How an SSD preserves logical addresses while relocating data, and why mapping policy, cache size and recovery guarantees need separate checks.
Glossary entry on hesela.dev · JSON record · Page-level mapping · Block-level mapping · Mapping-cache analysis · Metadata writeback · Recovery contracts
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In one minute
A flash translation layer maps host logical addresses to physical flash locations and manages flash-specific operations such as reclamation.
An overwrite can place new contents in a different flash page while keeping the host address unchanged. The map identifies the current location; the superseded page can remain physically programmed until its block is erased. Invalidation is not erasure. [1]
Before reclaiming a block, garbage collection preserves any still-live pages elsewhere. Wear leveling has a different objective: spreading erase wear. The policies interact, but reclaiming space and balancing wear are not interchangeable tasks. [1]
Mapping granularity and map residency are separate choices. Page-level mapping need not keep its entire table in RAM: DFTL selectively caches entries and stores translation pages in flash. Its Global Translation Directory locates those pages. [2]
In the demand-mapping architecture described by LearnedFTL, a cache miss can require a translation-page read before the requested data read. This dependency explains possible extra I/O, not a universal two-times latency multiplier: cache behavior, scheduling and other work also matter. [3]
Metadata writeback can add work beyond fetching a missing mapping; see the linked analysis. [2]
Recovery must reconstruct usable mappings and distinguish current data from obsolete copies. Agrawal and colleagues discuss persistent metadata and backup energy; these are design considerations, not proof that a particular SSD implements a specified crash contract. [1]
Raw flash can use a different stack. Linux UBIFS sits on UBI volumes over MTD; UBI provides wear leveling and bad-block management but still exposes flash erase semantics. It should not be described as a conventional block-device FTL. [4]
For a device investigation, record the model and firmware, access range, read/write mix and steady-state conditions. Check cache behavior separately from persistence guarantees, then use the linked analyses for mapping-footprint examples and explicit recovery models.
Mapping policies
These classical mapping schemes describe address translation, not the amount of RAM installed in a product.
Classical FTL mapping policies and their tradeoffs
- Page-level mapping
- Mapping ruleTracks each logical page independently. [2]
- TradeoffFlexible placement; a larger mapping representation.
- Block-level mapping
- Mapping ruleTranslates a logical flash block and retains the page offset. [2]
- TradeoffFewer entries; less flexible placement for small updates.
- Hybrid log-block mapping
- Mapping ruleCombines block-mapped data blocks with page-mapped update blocks. [2]
- TradeoffUpdate flexibility brings merge work.
Uncertainty notes
- Source-based engineering overview, not a device benchmark or reproduction of the cited papers.
- The older papers support mechanisms and terminology; their NAND geometry, timings and simulated speedups are not used as present-day product specifications.
Sources
- 01Agrawal et al. Design Tradeoffs for SSD Performance. USENIX ATC 2008, pp. 57-70, sections 3.1, 3.2 and 3.4. · accessed 2026-10-18
- 02Aayush Gupta, Youngjae Kim and Bhuvan Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. ASPLOS 2009, pp. 229-240, sections 2 and 3. DOI 10.1145/1508244.1508271. · accessed 2026-10-18
- 03Wang et al. LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs. HPCA 2024, pp. 616-629, sections II-III. DOI 10.1109/HPCA57654.2024.00054. · accessed 2026-10-18
- 04Linux kernel documentation: UBI File System, Introduction. · accessed 2026-10-18