Single-Level Cell NAND

SLC · one-bit NAND

One bit per cell, two states: native SLC, pseudo-SLC caching, and why burst write speed does not describe sustained SSD performance.

Glossary entry on hesela.dev · JSON record · pSLC mode · SLC cache

In one minute

SLC NAND stores one bit per cell using two distinguishable threshold-voltage states; native SLC media and single-bit operation on multi-bit-capable NAND must be distinguished.

KIOXIA explains that reads distinguish states using read-reference voltages between threshold-voltage distributions. SLC has two states; two-bit MLC, TLC and QLC have four, eight and sixteen. These counts describe data density, not a requirement for a floating-gate cell or a particular interface.

Native SLC is NAND designed for one-bit-per-cell storage. Pseudo-SLC (pSLC) instead operates supported multi-bit NAND in one-bit mode, as Swissbit explains. Swissbit's 2020 EN-26 announcement describes a full pSLC configuration. That is distinct from a temporary write cache; pSLC and SLC cache are not interchangeable names for every implementation.

A cache may use a fixed region, a dynamically sized region, or both. Valid data can be migrated into denser NAND to recover cache space. In Yoo and Shin's HotStorage 2020 study, allocation, update locality and garbage collection interact: a larger SLC region is not unconditionally faster. This is a trace-driven simulation, not a measurement of current retail SSDs.

Samsung's 860 QVO is a documented historical example. Its June 2019 whitepaper separates a 6 GB default buffer from an additional intelligent region. The October 2018 datasheet specifies up to 520 MB/s sequential writes with TurboWrite, but substantially lower rates after that region. The table below pairs those vendor specifications; it is not a Hesela benchmark or a prediction for other QLC products.

Migration is about surviving data, not every past write. In the paper, another update to the same address can invalidate an older cached version before migration; some requests can bypass the SLC region. This is why cache traffic alone does not specify the amount later programmed into QLC. The study also reports a workload where the learned policy performs similarly to the QLC-only baseline, so acceleration is not universal.

Cache capacity is not a recovery-time specification. Dividing buffer bytes by the post-cache host-write rate does not measure how long the controller takes to reclaim that buffer: migration, garbage collection and incoming writes may share resources. Treat any two-speed transfer-time calculation as an explicit simplified model, not a forecast or a measurement of this drive.

For an engineering comparison, record the exact drive capacity and firmware, starting fill, write volume, request pattern and queue depth, temperature, and idle time between runs. Report the throughput trace and post-cache interval separately. A short run inside the buffer cannot answer how a sustained workload behaves.

Compared to neighbors

SLC describes a cell mode; an SLC cache describes a role in the controller's data path. The following historical specifications demonstrate why cache size and post-cache speed belong next to the headline rate.

Samsung 860 QVO vendor specifications, not measurements: whitepaper Table 2 and datasheet page 5 note 3. GB and MB/s use decimal units; maximum listed buffer regions are not guaranteed available cache at every fill level.
Drive capacity	Buffer regions (GB)	After TurboWrite (MB/s)
1 TB	6 + 36 = 42	80
2 TB	6 + 72 = 78	160
4 TB	6 + 72 = 78	160

Strengths

Fewer states leave wider sensing margins than denser modes on comparable cells; this supports a performance/endurance trade-off, not a universal drive rating (KIOXIA).
Native SLC remains a component option for embedded and specialized systems; Micron maintains an SLC portfolio.
Supported pseudo-SLC modes can accelerate writes without requiring an SSD made entirely from native SLC media (Swissbit).

Limits

One-bit operation gives up capacity per cell compared with two-bit MLC, TLC or QLC.
A finite write buffer does not establish sustained throughput. Check performance after its region, not only the advertised burst figure.
SLC-mode NAND is not a DRAM cache. Neither the SLC label nor a cache-size figure establishes power-loss protection; controller metadata and in-flight writes remain separate concerns.
No universal endurance or retention number follows from the acronym. Qualify the actual component or drive and its operating conditions.

Typical fits

Native SLC components for qualified embedded designs
Supported pSLC configurations where capacity is traded for single-bit operation
Interpreting burst and post-cache SSD specifications

Uncertainty notes

Yoo and Shin model one 32 GB QLC chip and six traces, keep the mapping table in DRAM, and exclude reinforcement-learning execution overhead. No simulator speedup is generalized here.
Samsung's quoted rates are product-specific vendor results under the datasheet's test configuration. No SSD workload or power-cut experiment was performed for this card.
An SLC-cache performance claim does not establish successful recovery after power loss.

Sources

01Swissbit - EN-20 and EN-26 announcement, 6 August 2020, page 1 (full pSLC mode) · accessed 2026-10-16
02KIOXIA - Multi-level cell technology: threshold states and capacity · accessed 2026-10-16
03Swissbit - Storage technology, pSLC Mode and Powersafe sections · accessed 2026-10-16
04Micron - SLC NAND portfolio and embedded applications · accessed 2026-10-16
05Yoo and Shin - Reinforcement Learning-Based SLC Cache Technique for Enhancing SSD Write Performance, HotStorage 2020, sections 2 and 4 · accessed 2026-10-16
06Samsung - 860 QVO whitepaper, June 2019, page 4, Table 2 · accessed 2026-10-16
07Samsung - 860 QVO datasheet, Revision 1.0 (October 2018), page 5, notes 2-3 · accessed 2026-10-16