Quad-Level Cell NAND

Adding one bit from TLC to QLC doubles the number of states, not the stored data: four bits instead of three is a 4/3 encoding ratio. This is arithmetic at equal cell count. Manufacturing geometry, error-correction overhead and reserved capacity prevent it from being a prediction of a finished SSD's usable capacity.

Micron's selection guide includes enterprise use among QLC applications. That does not make every QLC SSD suitable for every database, nor does the acronym exclude databases categorically. The relevant evidence is the exact device's workload qualification, latency behavior and endurance.

Samsung's 870 QVO datasheet is a capacity-specific example. Its 530 MB/s sequential-write headline is cache-assisted; page 5 note 3 lists lower post-TurboWrite rates. These are vendor figures for this SATA family under its stated test setup, not inherent QLC speed limits.

Measure beyond the burst interval before judging a long ingest workload. Include starting fill and idle time in the test record so results from different cache states are not silently pooled. Cache space and migration activity are controller properties, not additional bits per cell.

Use the SSD's TBW or DWPD qualification rather than assigning one P/E count to QLC as a class. A lower write rate also says nothing by itself about recoverability after a power cut. Endurance, retention and recovery require separate evidence.

A less obvious QLC issue is an open NAND block. Papandreou et al. (IRPS 2020) found that a programming pause can leave pages with different stress histories; shared read-voltage calibration can then raise raw errors. This laboratory result is not a whole-drive failure rate.